1. Field of the Invention
The present invention relates to an image processing method for storing image data and more particularly to an image processing method in which image data is serially stored into a memory.
2. Description of the Related Art
In prior image processing systems, various types of image data, such as data of images on documents read by an image reader, image data as generated by personal computers (PC), and image data as received by facsimiles are appropriately processed and output in the form of a hard copy from an image output device. An arrangement of the image processing system is shown in FIG. 4.
In FIG. 4, a page memory 40, which temporarily stores image data, is used for various editing processes, such as "masking" for removing a part of an image, "trimming" for picking up only a part of an image, and "cut & paste" for cutting a specific image area out of a document and putting the image into a specific area on another document.
The image processing system shown in FIG. 4 includes PC 41, image read device 43, and facsimile machine 44, which can each generate digital image data, and the image output device 46. The image output device 46 is shared by the digital image data generating devices.
A PC 41 is provided which can typically have a keyboard and a pointing device (mouse) as input devices and a color CRT as an output device. Documents, figures, and tables are created using the PC 41. A bit mapping circuit 42 receives code data from the PC 41 and forms a bit map of the received code data.
Input image data can also be received from an image reader. An image reader 43 includes a line sensor typically constructed with CCDs, and a drive circuit. The image reader 43 outputs digital image data in which one picture element (pixel) consists of a preset number of bits.
Input image data also can be received from a facsimile machine. A facsimile machine 44 receives code data through a telephone line, such as code data specified by the CCITT, and converts it into image data.
An image output device 46 forms a hard copy output of the image by using the input image data from PC41, facsimile machine 44, or image read device 43. The image output device 46 is provided with a black developing unit, or if necessary, with a color developing unit.
A control device 45, which contains a microcomputer, controls in a supervisory manner the operations of the image processing system on the basis of controls at the user interface (abbreviated as UI, and not shown in FIG. 4), for example, by image processing the image data stored in the page memory.
In one case a copy job may be initiated at the UI and the corresponding image data generated by the PC 41 is outputted. The control device 45 transfers the image data as supplied from the PC 41, to the image output device 46. In this case, the data outputted from the PC 41, when it is bit map data, is directly applied to the image output device 46. When it is code data, it is applied to the bit mapping circuit 42 where it is converted into bit map data. The bit map data is then applied to the image output device 46.
In another case the copying job initiated at the UI may be to copy and output the image data as read by the image reader 43. The control device 45 receives the image data output from the image reader 43 and sends it to the image output device 46.
In the case where the job is to copy and output the image data received from the facsimile machine 44, the control device 45 transfers the image data as outputted from the facsimile 44 to the image output device 46. The facsimile decodes the received image data and converts it into bit map data.
When a mask edit instruction is given to mask a specific area in the image as read by the image read device, the control device 45 stores the image data from the image read device 43 into the page memory 40, stores it there, and then transfers the masked image data to the image output device 46. The same image processing steps are applied to the image data output from the PC 41 and the facsimile 44 if a mask edit instruction is given.
In the image processing system which handles the image data which as shown in FIG. 4, the number of bits of one pixel is not uniform. When the image data in which the number of bits is small is processed, only part of the page memory is used. In this case the system is not cost effective. The conventional page memory is based on a plane memory system. In the plane memory system, as shown in FIG. 5, the bits of the image data are stored into respective plane memories. For example, the least significant bit of the image data is stored in the least significant plane memory P0; the next bit Bl, in the plane memory Pl; and the most significant bit Bn, in the most significant plane memory Pn. When the image data output from the image reader 43 shown in FIG. 4 uses 3 bits for expressing one pixel, three plane memories of the page memory 40 are used. Where the page memory 40 stores the image data as derived from the image read device 43, the page memory is efficiently utilized. However, image data outputted from the bit mapping circuit 42 and from the facsimile machine 44 are the image data of two values, i.e., one bit for one pixel. Accordingly, when the page memory 40 stores such image data, only the least significant plane memory P0 of the page memory 40 is used, while the remaining plane memories are not used. In this respect, the cost effectiveness is not good.
There has been proposed another storing system in which image data is serially stored into a single plane memory (referred to as a serial memory system). In the serial memory system, as shown in FIG. 6(A), the image data of one bit for one pixel is stored in the following way. A value of the 0-th pixel as designated by "0" is stored in a memory location at a first address. A value of the first pixel as designated by "1" is stored in a memory location at a second address. A value of the second pixel as designated by "2" is stored in a memory location third address. Values of the subsequent pixels are stored into the memory locations of the subsequent addresses. In storing the image data of 3 bits for one pixel, as shown in FIG. 6(B), the least significant bit B.sub.0 of the 0-th pixel as designated by "0" is stored in the first address. The next bit B.sub.1 of the same pixel is stored into the memory location at the next address. The most significant bit B.sub. 2 is stored in the memory location of the next address. In this way, three bits B.sub.0, B.sub.1, and B.sub.2 of each pixel are serially stored in the address.
As described above, when the page memory comprises a serial pack storing system, it can effectively be used irrespective of the number of bits per pixel in the image data. Accordingly, the cost performance of the page memory can be improved.
In FIG. 6(B) showing a memory space of the page memory as "5B.sub.0 " indicates that the bit B.sub.0 of the fifth pixel is stored in the memory location at that address. The same is true for storage of other image data.
However, in the image processing system which employs the serial pack storing system for storing image data into the page memory, image processing in the memory space of the page memory is complicated and time consuming. This will be described by using as an example the edit instruction for "cut & paste".
The "cut & paste" edit is an image processing routine to place an image within a rectangular area 54 as defined by two points Q.sub.3 (x.sub.3, y.sub.3) and Q.sub.4 (x.sub.4, y.sub.4) of a second image 52, into a rectangular area 53 as defined by two points Q.sub.1 (x.sub.1, y.sub.1) and Q.sub.2 (x.sub.2, y.sub.2) of a first image 51, as shown in FIG. 7. For easy understanding, it is assumed here that x.sub.1 =x.sub.3, x.sub.2 =x.sub.4, y.sub.1 =y.sub.3, and y.sub.2 =y.sub.4, and that the rectangular areas 53 and 54 are each between the y.sub.1 th and y.sub.2 th lines and each include the pixels between the 47th pixel and the 78th pixel. For purposes of this example, it is assumed that the image data is designed such that one line consists of 4752 pixels and one pixel consists of 3 bits, and that the number of bits per access of the control device 45, viz., the number of bits of the data that the control device 45 can obtain through one time access, is 16 bits (constitutes one word). In the description to follow, the "cut & paste" image routine uses image data transferred to the memory space of the page memory.
It is assumed now that image data of a first image is written into a given memory area A in the page memory 40, and image data of a second image is written into another memory area B in the page memory 40, as shown in FIG. 8(A) (for simplicity only a single memory area is shown), in this case, the state "1" means the function, namely, the state "1" represents the pixel in black.
Under this condition, the control device 45 first fetches the image data of the 8-th word which corresponds to the y.sub.1 th line in the memory area B. The image data to be transferred is the image data of the 47th and subsequent pixels. Accordingly, the control device 45 prepares the following data EQU 0000000000000111.
The control device 45 logically multiplies the prepared data and the image data as previously fetched, which corresponds to the y.sub.1 th line in the memory area B, so that data of 42B.sub.2 to 46B.sub.2 are all set to "0", as shown in FIG. 8B.
Then, the control device 45 fetches the image data of the 8-th word at the address corresponding to the y.sub.1 th line in the memory area A, and prepares the following data EQU 1111111111111000.
The control device 45 logically multiplies the prepared data and the image data as previously fetched, which corresponds to the y.sub.1 th line in the memory area A, so that unnecessary image data of 47B.sub.0, 47B.sub.1, and 47B.sub.2 are all set to "0", as shown in FIG. 8C. Then, the control device 45 logically sums items of image data as shown in FIGS. 8(B) and 8(C), and stores the result of the logical sum into the memory location of the 8th word corresponding to the y.sub.1 th line in the memory area A.
Then, the control device 45 reads out the data of the 9th word at the address corresponding to the y.sub.1 th line in the memory area B, and then writes the read data into the memory location of the 9th word at the address corresponding to the y.sub.1 th line in the memory area A. This operation is repeated up to the 13th word.
Subsequently, the control device 45 reads out the data of the 14th word at the address corresponding to the y.sub.1 th line in the memory area B, and sets the unnecessary bit or bits to "0", as previously stated with reference to FIG. 8(D). Next, the control device 45 reads out the data of the 14th word at the address corresponding to the y.sub.1 th line in the memory area A, and sets the unnecessary bit or bits to "0", as previously stated with reference to FIG. 8(E). Then, the control device 45 logically sums those items of image data, and stores the result of the logical sum into the memory location of the 14th word corresponding to the y.sub.1 th line in the memory area A.
Consequently, the image data from the 47th pixel to the 78th pixel on the y.sub.1 th line in the memory area A is replaced by the image data of the second image. The above sequence of operations is repeated up to the y.sub.2 th line, to complete the image processing of the "cut & paste" edit.
When the serial pack storing system is used as described above, image data not required for the image processing is inevitably read out. Accordingly, the unnecessary data must be masked on every line and this impairs speed performance of the image processing.